----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    BCD_COUNTER 
-- Module Name:    BCD_COUNTER
-- Project Name:   Timer
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity BCD_COUNTER is
	generic(
		mod_value: INTEGER := 9
	);
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;
		i_count_carry_in: in STD_LOGIC;
		o_count: out STD_LOGIC_VECTOR (3 downto 0);	
		o_count_carry_out: out STD_LOGIC
	);
end entity BCD_COUNTER;

architecture behavior of BCD_COUNTER is
	signal r_count: STD_LOGIC_VECTOR (3 downto 0);
begin
	process(i_sys_rst,i_sys_clk,i_count_carry_in)	
		begin
			if (i_sys_rst = '1') then	
				r_count <= "0000";
				o_count_carry_out <= '0';
			elsif (i_sys_clk'event AND i_sys_clk = '1') then
				if (i_count_carry_in = '1') then
					if (r_count = mod_value) then
						r_count <= "0000";
						o_count_carry_out <= '1';
					else	
						r_count <= r_count +1;
						o_count_carry_out <= '0';
					end if;
				end if;	
			end if;
	end process;
	o_count <= r_count;
end architecture behavior;
